The present invention relates to a light emitting unit suitable as an image display unit or the like.
Light emitting diodes (LEDs) have been used as pixels of a light emitting unit such as an image display unit or a light source unit.
FIG. 10 shows a related art image display unit 10 of this type, wherein LED modules 2 are two-dimensionally arrayed on and fixed to a base body 1, and an anode electrode 3 and a cathode electrode 4 of each of the LED modules 2 are connected to wiring lines on the base body 1 by wire bonding or soldering.
The image display unit 10 has a screen including, for example, several hundreds of thousand pixels, wherein each of LED chips cut off from a wafer is used as the LED module 2 constituting one pixel. Such an image display unit 10, however, fails to increase the module density per unit area because of a large occupied area of the LED modules 2.
FIG. 11 is a plan view showing an essential portion of the image display unit 10, wherein the three kinds of LED modules 2 (for example, the LED module 2R for emission of red light, the LED module 2G for emission of green light, and the LED module 2B for emission of blue light) are arrayed on a plane of the base body 1, and a pixel transistor 5 for controlling the drive of the LED modules 2R, 2G, and 2B is fixedly connected to a position, apart from the LED modules 2R, 2G, and 2B, of the same plane of the base body 1. The pixel transistor 5 supplies specific control signals to the LED modules 2R, 2G, and 2B via wiring lines 6 and 7 (including wire bonding portions). Such a configuration of the image display unit 10 has an inconvenience that the pixel density cannot be increased due to not only the occupied area of the LED modules 2 but also the occupied area of the pixel transistor 5. Even if the pixel transistor 4 is disposed at the periphery of an image region, there is a limitation to improvement of the pixel density because of provision of a wiring region or the like.
To cope with such an inconvenience of the related art image display unit shown in FIG. 10, the resent applicant has already proposed, in Japanese Patent Application No. 2001-67238, a display unit capable of reducing an occupied area of semiconductor light emitting devices per unit area, simplifying wiring, and significantly reducing the fabrication cost.
This display unit according to the invention described in the earlier application (hereinafter, referred to as “earlier invention”) has a structure, for example, as shown in FIG. 12. Referring to FIG. 12, GaN based semiconductor light emitting devices 11, each of which is buried in a first insulating layer 21 made from epoxy region, are arrayed with a specific pitch on a plane of a transparent base body 31 taken as a display panel. In this case, each of the semiconductor light emitting devices 11 is fixed between connection electrodes 32 provided on the upper surface of the base body 31 via a transparent adhesive 33, and an epoxy region solution is applied to cover the overall surfaces of the semiconductor light emitting devices 11 and dried and heated to be cured, to form a second insulating layer 34 made from epoxy region.
In such a state, a connection hole 35 reaching an extraction electrode 18d of each semiconductor light emitting device 11 and a connection hole 36 reaching a connection electrode 32 on the upper surface of the base body 31 are formed in the second insulating layer 34, and a connection hole 37 reaching an extraction electrode 19d of the semiconductor light emitting device 11 is formed in the second insulating layer 34. After that, an aluminum layer is formed over the second insulating layer 34 so as to bury the holes 35, 36, and 37 by a vapor-deposition process of a sputtering process and is patterned by photolithography to form a conductive layer 38 part of which buries the connection holes 35 and 36 and a conductive layer 39, part of which buries the connection hole 37. As a result, a p-side electrode 18 (described later) of the semiconductor light emitting device 11 is connected to the connection electrode 32 on the base body 31 via the conductive layer 38 and is further connected to a drive control circuit, while an n-side electrode 19 (described later) of the semiconductor light emitting device 11 is led to the upper surface of the second insulating layer 34 via the conductive layer 39 and is further connected to another drive control circuit.
In this way, according to the display unit described in the earlier invention, the semiconductor light emitting devices 11, each of which is buried in the first insulating layer 21, are fixedly arrayed with a specific pitch on the plane of the base body 31 taken as a panel plane and covered with the second insulating layer 34, and the electrodes 18d and 19d of each of the semiconductor light emitting devices 11 are extracted via the conductive layers 38 and 39. As a result, it is possible to reduce the occupied area of the semiconductor light emitting devices per unit area of the display unit, simplify the wiring, and significantly reduce the fabrication cost.
Another advantage of the display unit described in the earlier invention is that since the GaN based semiconductor light emitting device 11 having a microsize is buried in the first insulating layer 21, to form a chip having a large apparent size, the handling of the light emitting device 11 can be facilitated. In addition, since the extraction electrodes 18d and 19d each having a relatively large area can be provided on the upper surface of the chip, that is, on the upper surface of the first insulating layer 21, it is easier to extract the electrodes to the second insulating layer 34 side.
The fabrication of each GaN based semiconductor light emitting device 11 used for the display unit described in the earlier invention will be described below.
FIGS. 13A and 13B are a sectional view and a plan view, respectively, showing a structure of the GaN based semiconductor light emitting device 11.
A buffer layer made from Al or GaN is formed on a (0001) plane of a sapphire substrate (not shown) at 500, and an n-type silicon-doped gallium nitride (GaN:Si) layer 12 is flatly grown thereon at 1000. A mask 13 made from SiO2 or SiN having an opening is formed on the silicon-doped GaN layer 12, and a hexagonal pyramid shaped n-type semiconductor (GaN:Si) layer 14 is formed by crystal growth of n-type silicon doped gallium nitride from the opening of the mask 13 at 1000° C.
An active layer 15 made from InGaN is formed on a (1-101) plane or a plane equivalent thereto of the hexagonal pyramid shape of the n-type semiconductor layer 14 at a growth temperature lower than 1000°, and a p-type magnesium-doped gallium nitride (GaN:Mg) 16 is grown on the active layer 15. A p-side electrode 18 made from Ni/Au, serving as a reflection plane from which light emitted from the active layer 15 is to be reflected, is formed on the p-type (GaN:Mg) layer 16 by vapor-deposition. Meanwhile, an opening is formed in the mask 13 on the flat under growth layer 12, and an n-side electrode 19 made from Ti/Au is formed on the under growth layer 12 through the opening formed in the mask 13 by vapor-deposition.
The semiconductor light emitting devices 11 thus formed are peeled from the sapphire substrate and are buried in a first insulating layer 21 (see FIG. 12) provided on a support body, and are peeled from the support body and transferred to a transparent support body. Extraction electrodes 18d and 19d (see FIG. 12) are then formed for each of the semiconductor light emitting devices 11. The first insulating layer 21 is diced into chips 40 each having a specific size. The dicing is made such that the semiconductor light emitting device 11 is located at an approximately central portion of the chip 40. Each chip 40 is irradiated with laser beams traveling from the back side of the transparent support body, to deteriorate the adhesive, thereby peeling the chip 40 from the transparent support body.
As shown in FIG. 12, the chips 40 are fixed to the transparent base body 31 and the second insulating layer 34 is formed to cover the chips 40, followed by the steps described above, to fabricate a display unit 41 shown in FIG. 12. It is to be noted that the semiconductor light emitting device 11 described above is configured as an LED but may be a semiconductor laser or the like (the same is true in the following description).
The extraction electrodes 18d and 19d, provided on each chip 40 having a large apparent size in which the semiconductor light emitting device 11 is buried, are connected to drive circuits. When a current is injected to each semiconductor light emitting device 11 of the display unit, the light emitting device 11 emits light rays 30 to the under growth layer 12 side or the transparent substrate 31 side.
The material of the semiconductor light emitting device 11 is not particularly limited insofar as it allows recombination of positive holes and electrons as carriers for light emission when a current is injected in the normal direction to a junction plane between the p-type semiconductor and the n-type semiconductor. The material may be a known semiconductor, examples of which include gallium based compound semiconductors such as gallium nitride (GaN) for emission of blue light, gallium phosphide (Gap) for emission of green light, gallium arsenic phosphide (GaAsp) for emission of red light, and aluminum gallium arsenide (AlGaAs), zinc selenide (ZnSe) and silicon carbide (SiC).
A compound semiconductor layer as part of the semiconductor light emitting device can be formed by an MOCVD (Metal-Organic Chemical Vapor Deposition) process, an MBE (Molecular Beam Epitaxy) process, or an HVpE (Hydride Vapor-phase Epitaxy) process. The size of the semiconductor light emitting device may be made as small as possible insofar as the device is handleable. Such a micro-sized semiconductor light emitting device can be easily obtained by a method of forming a compound semiconductor by selective crystal growth on a sapphire substrate as compared with a method of dicing a wafer made from a compound semiconductor into chips. A semiconductor light emitting device with its size of one side of a lower end surface being in a range of about 100 to 200 m or less (for example, about 10 to 50 m) can be obtained by such selective crystal growth. The device obtained by selective crystal growth may be subjected to additional processing for adjusting a three-dimensional shape.
In such a micro-sized semiconductor light emitting device formed by selective crystal growth, a p-side electrode made from, for example, Ni/Au is formed on the p-type semiconductor by vapor-deposition and an n-side electrode made from Ti/Au is formed on the n-type semiconductor by vapor-deposition. Each micro-sized semiconductor light emitting device provided with these electrodes may be fixedly arrayed on the surface of a base body as it is. However, the semiconductor light emitting device formed into a significantly micro-shape is, as described above, covered with a first insulating layer to form a chip having a large apparent size. This is advantageous in facilitating the handling of the semiconductor light emitting device.
Each semiconductor light emitting device 11 fixedly arrayed on a transparent base body is allowed to improve the luminance of emission light to the base body plane side; that is, the lower end surface side of the semiconductor light emitting device depending on the shape thereof. Of light emitted from a light emission region (active layer) of the semiconductor light emitting device 11, a light component traveling upwardly from the light emission region is reflected from an electrode plane taken as a reflection plane of the upper end portion to the lower end surface side. However, a light component traveling to a side surface perpendicular to the lower end surface less travels to the lower end surface side even if being reflected from the side surface. In this regard, it is desired for the semiconductor light emitting device 11 to have a tilt plane tilted from the lower end surface at an angle in a range of 45±20°. By providing a reflection plane on such a tilt plane, the light component traveling to the side surface can be effectively reflected therefrom to the lower end surface side.
The tile plane may be a one-side tilt plane, a both-side tilt plane, or a square tilt plane. With respect to reflection of emission light, the semiconductor light emitting device preferably has a pyramid shape or a truncated pyramid shape. In particular, for the semiconductor light emitting device having a truncated pyramid shape, such as a polygonal truncated pyramid shape, the upper surface can be taken as a reflection plane, whereby light emitted from the active layer can be more effectively directed to the lower end surface side. The term “pyramid shape” includes a triangular pyramid shape, a square pyramid shape, a pentagonal pyramid shape, a hexagonal pyramid shape, and a polygonal pyramid shape close to a cone, and the term “truncated pyramid shape” includes truncated pyramid shapes corresponding to the above-described various pyramid shape.
The material used for each of the insulating layers such as the first insulating layer 21 and the second insulating layer 34 may be either an organic material or an inorganic material, with the kind and formation method thereof being particularly limited. In the case of using SiO2 or Si3O4 as an inorganic material, it may be formed by a CVD (Chemical Vapor Deposition) process or a sputtering process. In the case of using a polymer compound such as epoxy resin, polyimide resin, or synthetic rubber as an organic material, it can be easily formed even on a base body having a large area by a simple coating process, thereby reducing the cost of a display unit. As an insulating layer formed by coating, a glass film coated by a spin-on-glass process is usable.
The display unit described in the earlier invention having the above-described advantages, however, has a problem to be improved.
In the display unit described in the earlier invention, a pixel transistor (not shown, which is equivalent to the transistor 5 shown in FIG. 11) for controlling the drive of the chips (LIP) 40 in each of which the semiconductor light emitting device 11 is buried is disposed on the base body 31 at a position, apart from the chips 40, on the same plane as that on which the chips 40 are disposed, so that as described above, the pixel density cannot be increased so much due to the occupied area of the pixel transistor. Even if the pixel transistor is disposed at the periphery of an image region, there is a limitation to improvement of the pixel density because of provision of a wiring region or the like.
Another disadvantage of the display unit described in the earlier invention is that since there is a limitation to the area of a panel (area of an image portion) of the display unit, the size of each chip 40 must be reduced due to the occupied area of the pixel transistor. Accordingly, the diameters of the connection holes 35 and 37 (via-holes) become small, to cause inconveniences that alignment accuracy must be increased at the time of bonding each chip or device, and that a stress produced by thermal expansion or contraction of the insulating layers 21 and 34 causes strains of the connection holes (via-holes) 35 and 37, which may possibly lead to disconnection.